VLSI design 101 - The test module

VLSI, MCM, and WSI: A Design Comparison

A Novel Hierarchical Test Generation Method for Processors

Raghuram S. Tupuri Advanced Processor Development Advanced Micro devices Austin TX 78741 Jacob A. Abraham Computer Engineering Research Center University of Texas at Austin Austin TX 78752 same coverage is obtained. Figure 1 illustrates the proposed hierarchical test generation process using a commercially available test generator. This paper describes a novel method for hierarchical functional...

Design and Implementation of Digital Demodulator for Frequency Modulated CW Radar (RESEARCH NOTE)

Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to...

Cost Modeling for SOC Modules Testing

The complexity of the system design is increasing very rapidly as the number of transistors on Integrated Circuits (IC) doubles as per Moore’s law. There is big challenge of testing this complex VLSI circuit, in which whole system is integrated into a single chip called System on Chip (SOC). Cost of testing the SOC is also increasing with complexity. Cost modeling plays a vital role in reductio...

Register-transfer level fault modeling and test evaluation techniques for VLSI circuits

Stratified fault sampling is used in RTL fault simulation to estimate the gate-level fault coverage of given test patterns. RTL fault modeling and fault injection algorithm are developed such that the RTL fault list of a module can be treated as a representative fault sample of the collapsed stuck-at fault set of the module. The RTL coverage for the module is experimentally found to track the g...